PV Cell Processing Line

Technology Routes

Three architectures, three different lines

These are not variants of one line. The technology route sets the thermal budget, the cleanliness class, the deposition toolset and the metallisation method, and it constrains how the finished cells can be interconnected into modules. Choosing it is the first engineering decision, not a later configuration option.

Cross-section comparison of TOPCon, HJT and back contact cell architectures

Route Comparison

Choosing between TOPCon, HJT and BC

Indicative industry ranges for engineering discussion. Achievable figures depend on wafer quality, equipment selection and process maturity.
Criterion	TOPCon	HJT	BC
Cell efficiency	25.0 – 26.5%	25.0 – 26.5%	26.0 – 27.5%
Process temperature	High (> 800 °C steps)	Low (< 200 °C throughout)	Depends on base route
Process steps	More, around 12–14	Fewer, around 6–8	Most, patterning added
Bifaciality	≈ 0.80 – 0.85	≈ 0.90 – 0.95	Varies by design
Temperature coefficient	Good	Best in class	Good to very good
Cleanliness demand	Standard cell-line class	Very high, surface critical	High
Silver consumption	Moderate	Higher (low-temp paste) or Cu plating	Route dependent
Indium / TCO need	None	Yes, ITO or IWO sputtering	Route dependent
Module interconnection	Conventional soldering	Low-temperature methods only	Specialised, often 0BB
Relative line capex	Lowest of the three	Higher, PECVD and PVD heavy	Highest, precision patterning
Best fit	Capacity scale-up with contained risk	Hot climates, high energy yield, bifacial	Premium efficiency and aesthetics

M10 at 182 mm and G12 at 210 mm wafers drawn to scale with a half-cut division line, and four front-side metallisation routes from 5BB through 9BB and 16BB to busbar-free rear contact — What the line has to accept on either side of that table. Format and busbar count have moved faster than equipment depreciates, so we specify with headroom rather than at the limit: 182 mm optimal and 210 mm compatible, multi-busbar through to the 0BB routes BC designs need, half-cut and bifacial throughout.

Route 01

TOPCon process line

Tunnel oxide passivated contact. A thin tunnel oxide plus doped polysilicon layer on the rear delivers excellent surface passivation while still allowing carrier extraction, reached through a largely conventional high-temperature process route.

TexturingAlkaline texturing to reduce front surface reflection; pre-cleaning.

Boron diffusionBBr₃ or BCl₃ tube diffusion forming the p+ emitter on the front surface.

BSG removal & etchBorosilicate glass removal and single-side etching of parasitic layers.

Tunnel oxide growthUltra-thin SiOₓ tunnel oxide, thickness controlled to roughly 1–2 nm.

Poly-Si depositionLPCVD, PECVD or PEALD polysilicon with in-situ or ex-situ phosphorus doping.

Wrap-around removalSelective etch or alkaline polish to remove parasitic poly from front and edges.

Front passivationALD AlOₓ followed by PECVD SiNₓ as passivation and anti-reflection stack.

Rear coatingPECVD SiNₓ capping over the poly-Si contact layer.

MetallisationScreen printing of front and rear pastes; fine-line and busbar definition.

Fast firingHigh-throughput belt furnace firing to form contacts through the dielectric.

Test & sortI-V measurement to IEC 60904, electroluminescence inspection, binning.

Where TOPCon lines are usually won or lost

Tunnel oxide thickness uniformity and the completeness of wrap-around poly removal drive both efficiency and yield. Both are equipment and process-control problems rather than material problems, which is why they belong in the line engineering specification.

Route 02

HJT process line

Silicon heterojunction. Thin intrinsic and doped amorphous silicon films passivate the crystalline wafer on both sides, with transparent conductive oxide carrying current laterally to the metal grid. Fewer steps than TOPCon, but every step is more demanding.

Ultra-clean texturingAlkaline texturing with tightly controlled metallic contamination limits.

Final surface cleanOzone or RCA-type cleaning sequence; surface condition is decisive here.

Intrinsic a-Si:HPECVD deposition of the intrinsic passivation layer on both surfaces.

Doped a-Si:HPECVD p-type and n-type layers completing the heterojunction, below 200 °C.

TCO sputteringPVD deposition of ITO or IWO on both sides for lateral conduction.

MetallisationLow-temperature silver paste screen printing, or copper electroplating.

Low-temperature cureCuring below the amorphous silicon damage threshold, typically under 200 °C.

Test & sortI-V measurement, EL inspection and binning with bifacial characterisation.

Why fewer steps is not simply cheaper

HJT removes high-temperature diffusion and firing, but adds PECVD capacity, TCO sputtering with indium consumption, and low-temperature silver paste or a plating line. Capital and consumable cost shift rather than disappear.

Where HJT pays back

The temperature coefficient is the best of the three routes and bifaciality is the highest, so energy yield in hot and high-albedo installations can exceed what the nameplate efficiency comparison suggests.

Route 03

BC process line

Back contact. Moving all metallisation to the rear removes front-surface shading entirely, which lifts the efficiency ceiling and produces a uniform black module face. BC is an architecture rather than a passivation scheme, it can be built on a TOPCon base (TBC) or an HJT base (HBC).

Texturing & cleanFront texturing optimised for optical performance with no metal shading to consider.

Front passivationAlOₓ and SiNₓ stack across the entire illuminated surface.

Rear patterningPrecision laser ablation or masking to define interdigitated p+ and n+ regions.

DopingFormation of the alternating emitter and back surface field regions.

Rear passivationPassivation of the patterned rear with isolation between polarities.

Contact openingPrecisely aligned laser opening of contact windows in each region.

MetallisationInterdigitated rear metallisation carrying both polarities without crossing.

Test & sortI-V measurement, EL inspection, tight alignment and isolation verification.

The engineering constraint to plan for

BC lines live and die on alignment accuracy and shunt control between adjacent polarities. Laser precision, stage accuracy and inline inspection capability need specifying tighter than on either TOPCon or HJT, and the module line must be designed for BC interconnection from the start, since conventional stringing does not apply.

Three architectures, three different lines

Choosing between TOPCon, HJT and BC

TOPCon process line

Where TOPCon lines are usually won or lost

HJT process line

Why fewer steps is not simply cheaper

Where HJT pays back

BC process line

The engineering constraint to plan for

Cell technology drives module design

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PV Module Line

Integrated Automation

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